View ACPL-C87B-500E_6933149.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

acpl-c87b, acpl-c87a, acpl-c870 precision optically isolated voltage sensor data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. features ?? advanced sigma-delta ( ? - ? ) modulation technology ?? unity gain 1 v/v, 0.5% high gain accuracy (acpl-c87b) ?? 1 g ? input impedence ?? 0 to 2 v nominal input range ?? -35 ppm/c low gain drift ?? 21 ? v /c off set voltage drift ?? 0.1% non-linearity max ?? active-high shutdown pin ?? 100 khz wide bandwidth ?? 3 v to 5.5 v wide supply range for output side ?? -40 c to +105 c operating temperature range ?? 15 kv/ ? s common-mode transient immunity ?? compact, auto-insertable stretched so-8 package ?? safety and regulatory approvals (pending): C iec/en/din en 60747-5-5: 1230 vpeak working insulation voltage C ul 1577: 5000 vrms/1 min double protection rating C csa: component acceptance notice #5 applications ?? isolated voltage sensing in ac and servo motor drives ?? isolated dc-bus voltage sensing in solar inverters, wind turbine inverters ?? isolated sensor interfaces ?? signal isolation in data acquisition systems ?? general purpose voltage isolation description the acpl-c87b/c87a/c870 voltage sensors are optical isolation amplifi ers designed specifi cally for voltage sensing. its 2 v input range and high 1 g ? input impe- dance, makes it well suited for isolated voltage sensing requirements in electronic power converters applications including motor drives and renewable energy systems. in a typical voltage sensing implementation, a resistive voltage divider is used to scale the dc-link voltage to suit the input range of the voltage sensor. a diff erential output voltage that is proportional to the input voltage is created on the other side of the optical isolation barrier. for general applications, the acpl-c87a (1% gain tolerance) and the acpl-c870 (3% gain tolerance) are recommended. for high precision requirements, the acpl-c87b (0.5% gain tolerance) can be used. the acpl-c87b/c87a/c870 family operates from a single 5 v supply and provides excellent linearity. an active-high shutdown pin is available which reduces the idd1 current to only 15 ? a, making them suitable for battery-powered and other power-sensitive applications. the high common-mode transient immunity (15 kv/ ? s) of the acpl-c87b/c87a/c870 provides the precision and stability needed to accurately monitor dc-link voltage in high noise environments. combined with superior optical coupling technology, the acpl-c87b/c87a/c870 imple- ments sigma-delta ( ? - ? ) modulation, chopper stabilized amplifi ers, and diff erential outputs to provide unequaled isolation-mode noise rejection, low off set, high gain accuracy and stability. this performance is delivered in a compact, auto-insertable stretched so-8 (sso-8) package that meets worldwide regulatory safety standards. lead (pb) free rohs 6 fully compliant rohs 6 full y compliant options available; -xxxe denotes a lead-f r ee p r oduct
2 ordering information acpl-c87b/c87a/c870 is ul recognized with 5000 vrms/1 minute rating per ul 1577 (pending). table 2. part number option package surface mount tape & reel iec/en/din en 60747-5-5 quantity (rohs compliant) acpl-c87b acpl-c87a acpl-c870 -000e stetched so-8 x x 80 per tube -500e x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example: acpl-c87a-500e to order product of surface mount package in tape and reel packaging with iec/en/din en 60747-5-5 safety approval and rohs compliance. contact your avago sales representative or authorized distributor for information. functional diagram gnd2 v dd2 v out+ v outC v dd1 gnd1 shield v in 1 2 3 4 5 6 7 8 shdn figure 1. table 1. pin description pin no. symbol description 1v dd1 supply voltage for input side (4.5 v to 5.5 v), relative to gnd1 2v in voltage input 3 shdn shutdown pin (active high) 4 gnd1 input side ground 5 gnd2 output side ground 6v out- negative output 7v out+ positive output 8v dd2 supply voltage for output side (3 v to 5.5 v), referenced to gnd2 note: a 0.1 ? f bypass capacitor must be connected between pins 1 and 4 and between pins 5 and 8.
3 5.850 0.254 (0.230 0.010) 5 6 7 8 4 3 2 1 dimensions in millimeters and (inches). note: lead coplanarity = 0.1 mm (0.004 inches). floating lead protrusion = 0.25mm (10mils) max. 6.807 0.127 (0.268 0.005) recommended land pattern 12.650 (0.498) 1.905 (0.075) 3.180 0.127 (0.125 0.005) 0.381 0.127 (0.015 0.005) 1.270 (0.050) bsg 7 0.254 0.100 (0.010 0.004) 0.750 0.250 (0.0295 0.010) 11.50 0.250 (0.453 0.010) 1.590 0.127 (0.063 0.005) 0.450 (0.018) 45 rohs-compliance indicator 0.64 (0.025) 0.200 0.100 (0.008 0.004) package outline drawing stretched so-8 package (sso-8) figure 2. sso-8 package recommended pb-free ir profi le recommended refl ow condition as per jedec standard, j-std-020 (latest revision). non-halide flux should be used. regulatory information the acpl-c87b/c87a/c870 is pending approval by the following organizations: iec/en/din en 60747-5-5 approval with maximum working insulation voltage v iorm = 1230 vpeak. ul approval under ul 1577, component recognition program up to v iso = 5000 vrms/1 min. file 55361. csa approval under csa component acceptance notice #5, file ca 88324 part number date code c87b yww
4 table 3. insulation and safety related specifi cations parameter symbol value unit conditions minimum external air gap (external clearance) l(101) 8.0 mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (external creepage) l(102) 8.0 mm measured from input terminals to output terminals, shortest distance path along body minimum internal plastic gap (internal clearance) 0.5 mm through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity tracking resistance (comparative tracking index) cti > 175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) table 4. iec/en/din en 60747-5-5 insulation characteristics [1] description symbol value units installation classifi cation per din vde 0110/1.89, table 1 for rated mains voltage 150 vrms for rated mains voltage 300 vrms for rated mains voltage 450 v rms for rated mains voltage 600 vrms for rated mains voltage 1000 vrms i-iv i-iv i-iv i-iv i-iii climatic classifi cation 55/105/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage (pending qualifi cation) v iorm 1230 vpeak input to output test voltage, method b v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc v pr 2306 vpeak input to output test voltage, method a v iorm x 1.6 = v pr , type and sample test, t m = 10 sec, partial discharge < 5 pc v pr 1968 vpeak highest allowable overvoltage (transient overvoltage, t ini = 60 sec) v iotm 8000 vpeak safety-limiting values (maximum values allowed in the event of a failure) case temperature input current [2] output power [2] t s i s,input p s,output 175 230 600 c ma mw insulation resistance at t s , v io = 500 v r s 10 9 ? notes: 1. insulation characteristics are guaranteed only within the safet y maximum ratings, which must be ensured by protective circui ts within the application.
5 table 5. absolute maximum rating parameter symbol min. max. units storage temperature t s -55 +125 c ambient operating temperature t a -40 +105 c supply voltage v dd1 , v dd2 -0.5 6.0 v steady-state input voltage [1, 3] v in -2 v dd1 + 0.5 v two-second transient input voltage [2] v in -6 v dd1 + 0.5 v logic input v sd -0.5 v dd1 + 0.5 v output voltages v out+ , v out? -0.5 v dd2 + 0.5 v lead solder temperature 260 c for 10 sec., 1.6 mm below seating plane notes: 1. dc voltage of up to -2 v on the inputs does not cause latch-up or damage to the device. 2. transient voltage of 2 seconds up to -6 v on the inputs does not cause latch-up or damage to the device. 3. absolute maximum dc current on the inputs = 100 ma, no latch-up or device damage occurs. table 6. recommended operating conditions parameter symbol min. max. units ambient operating temperature t a -40 +105 c v dd1 supply voltage v dd1 4.5 5.5 v v dd2 supply voltage v dd2 3.0 5.5 v input voltage range [1] v in 0 2.0 v shutdown enable voltage v sd v dd1 C 0.5 v dd1 v notes: 1. 2 v is the nominal input range. full scale input range (fsr) is 2.46 v.
6 table 7. electrical specifi cations unless otherwise noted, t a = -40 c to +105 c, v dd1 = 4.5 v to 5.5 v, v dd2 = 3.3 v to 5.5 v, v in = 0 C 2 v, and v sd = 0 v. parameter symbol min. typ. [1] max. unit test conditions/notes fig. dc characteristics input off set voltage v os -9.9 -0.3 9.9 mv t a = 25 c 3, 4 magnitude of input off set change vs. temperature |dv os /dt a |21 ? v/c t a = C40 c to +105 c ; direct short across inputs. 5 gain (acpl-c87b, 0.5%) g0 0.995 1 1.005 v/v t a = 25 c; v dd2 = 5 v; note 2. 6, 7 0.994 0.999 1.004 v/v t a = 25 c; v dd2 = 3.3 v; note 2. 6, 7 gain (acpl-c87a, 1%) g1 0.99 1 1.01 v/v t a = 25 c; note 2. 6, 7 gain (acpl-c870, 3%) g3 0.97 1 1.03 v/v t a = 25 c; note 2. 6, 7 magnitude of gain change vs. temperature dg/dt a -35 ppm/c t a = -40 c to +105 c 8 nonlinearity nl 0.05 0.1 % v in = 0 to 2 v, t a = 25 c 9, 10 magnitude of nl change vs. temperature |dnl/dt a | 0.0002 %/c t a = -40 c to +105 c 11 inputs and outputs recommended input range vinr 2 v referenced to gnd1 full-scale diff erential voltage input range fsr 2.46 v referenced to gnd1 shutdown logic low input voltage v il 0.8 t a = 25 c shutdown logic high input voltage v ih v dd C 0.5 5 t a = 25 c input bias current i in -0.1 -0.0015 ? a v in = 0 v magnitude of i in change vs. temperature di in /dt a 1 na/c equivalent input impedance r in 1000 m ? output common-mode voltage v ocm 1.23 v v out+ or v outC output voltage range voutr vocm 1.23 vv sd = 0 v. note 4. 13 output short-circuit current |i osc |30mav out+ or v outC , shorted to gnd2 or v dd2 output resistance r out 36 ? v out+ or v outC
7 table 7. electrical specifi cations (continued) unless otherwise noted, t a = -40 c to +105 c, v dd1 = 4.5 v to 5.5 v, v dd2 = 3.3 v to 5.5 v, v in = 0 C 2 v, and v sd = 0 v. parameter symbol min. typ. [1] max. unit test conditions/notes fig. ac characteristics vout noise n out 0.013 mv rms vin = 0 v; output low-pass fi ltered to 180 khz. note 3. 12 small-signal bandwidth (-3 db) f C3 db 70 100 khz guaranteed by design input to output propagation delay 50%-10% t pd10 2.2 3.0 ? s step input. 18 50%-50% t pd50 3.7 5.5 ? s step input. 18 50%-90% t pd90 5.3 6.5 ? s step input. 18 output rise/fall time (10%-90%) t r/f 2.7 4.0 ? s step input (t pd90 - t pd10 ) shutdown delay t sd 25 40 ? s vin = 2 v 17 enable delay t on 150 200 ? s common mode transient immunity cmti 10 15 kv/ ? s v cm = 1 kv, t a = 25 c power supply rejection psr -78 db 1 vpp 1 khz sine wave ripple on v dd1 , diff erential output power supplies input side supply current i dd1 10.5 15 ma v sd = 0 v 15 ? a v sd = 5 v i dd2 6.5 12 ma 5 v supply 6.1 11 ma 3.3 v supply notes: 1. all typical values are under typical operating conditions at t a = 25 c, v dd1 = 5 v, v dd2 = 5 v. 2. gain is defi ned as the slope of the best-fi t line of diff erential output voltage (v out+ C v out- ) versus input voltage over the nominal range, with off set error adjusted. 3. noise is measured at the output of the diff erential to single ended post amplifi er. 4. when is v sd = 5 v or when shutdown is enabled, v out+ is close to 0v and v out- is at close to 2.46 v. this is similar to when vdd1 is not supplied. table 8. package characteristics parameter symbol min typ max units test conditions note input-output momentary withstand voltage v iso 5000 vrms rh < 50%, t = 1 min., t a = 25 c 1, 2 resistance (input-output) r i-o > 10 12 ? v i-o = 500 v dc 3 capacitance (input-output) c i-o 0.5 pf f = 1 mhz 3 notes: 1. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 6000 vrms for 1 second (leakage detection current limit, i i-o 5 ma). this test is performed before the 100% production test for partial discharge (method b) shown in iec/en/din en 60747- 5-5 insulation characteristic table. 2. the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-outpu t continuous voltage rating. for the continuous voltage rating, refer to the iec/en/din en 60747-5-5 insulation characteristics table and yo ur equipment level safety specifi cation. 3. this is a two-terminal measurement: pins 1C4 are shorted together and pins 5C8 are shorted together.
8 -5 -4 -3 -2 -1 0 1 2 3 4 5 4.5 5 5.5 offset (mv) vdd1(v) -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 3 3.5 4 4.5 5 5.5 offset (mv) vdd2 (v) offset (mv) temp ( q c) 0.997 0.998 0.999 1.000 1.001 1.002 1.003 4.5 5 5.5 gain (v/v) vdd1 (v) 0.997 0.998 0.999 1.000 1.001 1.002 1.003 3 3.5 4 4.5 5 5.5 gain (v/v) vdd2 (v) 0.99700 0.99800 0.99900 1.00000 1.00100 1.00200 1.00300 -55 -35 -15 5 25 45 65 85 105 125 gain (v/v) temp ( q c) -10 -8 -6 -4 -2 0 2 4 6 8 10 -55 -35 -15 5 25 45 65 85 105 125 m+3 mean m- 3 figure 3. input off set vs supply vdd1 figure 4. input off set vs supply vdd2 figure 5. input off set vs temperature figure 6. gain vs supply vdd1 figure 7. gain vs supply vdd2 figure 8. gain vs temperature typical performance plots all 3(sigma symbol) plots are based on characterization test r esult at the point of product release. for guaranteed specifi cation, refer to the respective electrical specifi cations section.
9 -6 -5 -4 -3 -2 -1 0 1 1000 10000 100000 gain (db) bandwidth (hz) vin = 0 v vin = 1 v vin = 2 v 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -55 -35 -15 5 25 45 65 85 105 125 nl (%) temp ( q c) -1 1 3 5 7 9 11 13 15 17 0 20 40 60 80 100 120 140 160 ac noise (vrms) freq filter (khz) v out+ v outC 0 0.5 1 1.5 2 2.5 3 v out+ , v outC 0 0.5 1 1.5 2 2.5 3 v in 0 0.02 0.04 0.06 0.08 0.1 4.5 5 5.5 nl (%) vdd1 (v) 0 0.02 0.04 0.06 0.08 0.1 3 3.5 4 4.5 5 5.5 nl (%) vdd2 (v) figure 9. non-linearity vs supply vdd1 figure 10. non-linearity vs supply vdd2 figure 11. non-linearity vs temperature figure 12. ac noise vs filter freq vs vin figure 13 v in vs v out+ , v out- figure 14. frequency response
10 figure 15. phase response figure 16. propagation delay vs temperature figure 18. input to output propagation delay timing diagram. v out diff = v out+ - v out- figure 17. shutdown and wakeup input to output timing diagram. v out diff = v out+ - v out- vin v sd v out diff +2 v -2.46 v 0 v 0 v 2 v 0 v 5v t sd t on v in v out diff 0 v 2 v 0 v 2 v t plh50-10 t plh50-50 t plh50-90 tplh 50-10 tplh 50-50 tplh 50-90 0 20 40 60 80 100 120 140 160 180 200 1000 10000 100000 phase (deg) bandwidth (hz) 0 1 2 3 4 5 6 -55 -35 -15 5 25 45 65 85 105 125 prog delay ( p s) temp ( q c)
11 figure 19. typical application circuit. defi nitions gain gain is defi ned as the slope of the best-fi t line of diff eren- tial output voltage (v out+ C v out- ) over the nominal input range, with off set error adjusted out. nonlinearity nonlinearity is defi ned as half of the peak-to-peak output deviation from the best-fi t gain line, expressed as a per- centage of the full-scale diff erential output voltage. common mode transient immunity, cmti, also known as common mode rejection cmti is tested by applying an exponentially rising/falling voltage step on pin 4 (gnd1) with respect to pin 5 (gnd2). the rise time of the test waveform is set to approximately 50 ns. the amplitude of the step is adjusted until the dif- ferential output (v out+ C v out- ) exhibits more than a 200 mv deviation from the average output voltage for more than 1s. the acpl-c87x will continue to function if more than 10 kv/ ? s common mode slopes are applied, as long as the breakdown voltage limitations are observed. power supply rejection, psr psrr is the ratio of diff erential amplitude of the ripple outputs over power supply ripple voltage, referred to the input, expressed in db. application information application circuit the typical application circuit is shown in figure 19. the acpl-c87x voltage sensor is often used in photo- voltaic (pv) panel voltage measurement and tracking in pv inverters, and dc bus voltage monitoring in motor drivers. the high voltage across rails needs to be scaled down to fi t the input range of the iso-amp by choosing r1 and r2 values according to appropriate ratio. the acpl-c87x senses the single-ended input signal and produces diff erential outputs across the galvanic isolation barrier. the diff erential outputs (vout+, vout-) can be connected to an op-amp to convert to a single- ended signal or directly to two adcs. the op-amp used in the external post-amplifi er circuit should be of suffi ciently high precision so that it does not contribute a signifi cant amount of off set or off set drift relative to the contribu- tion from the isolation amplifi er. generally, op-amps with bipolar input stages exhibit better off set performance than op-amps with jfet or mosfet input stages. in addition, the op-amp should also have enough bandwidth and slew rate so that it does not adversely aff ect the response speed of the overall circuit. the post- amplifi er circuit includes a pair of capacitors (c4 and c5) that form a single-pole low-pass fi lter; these capacitors allow the bandwidth of the post-amp to be adjusted in- dependently of the gain and are useful for reducing the output noise from the isolation amplifi er. the gain-setting resistors in the post-amp should have a tolerance of 1% or better to ensure adequate cmrr and adequate gain tolerance for the overall circuit. resistor networks can be used that have much better ratio toler- ances than can be achieved using discrete resistors. a resistor network also reduces the total number of compo- nents for the circuit as well as the required board space. v dd1 1 v in 2 shdn 3 gnd1 4 gnd2 5 v out- 6 v out+ 7 v dd2 8 u1 acpl-c87x gnd2 r4 10k,1% gnd2 v dd2 v dd1 vout gnd1 l1 l2 r2 10k c1 100 pf c2 100 nf c3 100 nf r3 10k,1% r1 u2 opa237 v+ v- c4 100 pf r5 10k, 1% c5 100 pf r6 10k, 1%
12 the input stage of the typical application circuit in figure 19 can be simplifi ed as the diagram shown in figure 20. r2 and r in , input resistance of the acpl-c87x, create a current divider that results in an additional measurement error component that will add on to the tot on top of the device gain error. with the assumption that r1 and r in have a much higher value than r2, the resulting error can be estimated to be r2/r in . with r in of 1 gw for the acpl-c87x, this additional mea- surement error is negligible with r2 up to 1 m ? , where the error is approximately 0.1%. though small, it can be further reduced by reducing the r2 to 100 k ? (error of 0.01% approximately), or 10 k ? (error of 0.001% approximately). however with lower r2, a drawback of higher power dis- sipation in the resistive divider string needs to be consid- ered, especially in higher voltage sensing applications. for example, with 600 v dc across l1 and l2 and r2 of 100 k ? for 0.01% measurement error, the resistive divider string figure 20. simplifi ed input stage. figure 21. thermistor sensing in igbt module consumes about 12 mw, assuming v in is set at 2 v. if the r2 is reduced to 10 k ? to reduce error to 0.001%, the power consumption will increase to about 120 mw. in energy effi ciency critical applications such as pv inverters and battery-powered applications, this trade-off between measurement accuracy and power dissipation in the resistive string provides fl exibility in design priority. isolated temperature sensing using thermistor igbts are an integral part of a motor or servo drive system and because of the high power that they usually handle, it is essential that they have proper thermal management and are suffi ciently cooled. long term overload conditions could raise the igbt module temperature permanently or failure of the thermal management system could subject the module to package overstress and lead to catastrophic failures. one common way to monitor the temperature of the module is through using a ntc type thermistor mounted onto the igbt module. some igbt module man- ufacturers also have igbts that comes with the thermistor integrated inside the module. in some cases, it is necessary to isolate this thermistor to provide added isolation and insulation due to the high power nature of the igbts. the acpl-c87x voltage sensor can be used to easily meet such a requirement, while providing good accuracy and non-linearity. figure. 21 shows an example of such an implementation. the acpl-c87x is used to isolate the thermistor voltage which is later fed by the post amp stage to an adc onboard the microcontroller (mcu) to determine the module temperature. the thermistor needs to be biased in way that its voltage output will optimize the 2 v input range of the acpl-c87x across the intended temperature measurement range. measurement accuracy and power dissipation of the resistive divider + C + gnd acpl-c87x r1 r2 r in hv+ hv- igbt module ntc thermistor u v w + C + gnd acpl-c87x vdd mcu adc post amp
13 figure 22. recommended power supply and bypassing power supplies and bypassing a power supply of 5 v is required to power the acpl-c87x input side vdd1. in many motor drive dc bus voltage sensing applications, this 5 v supply is most often obtained from the same supply used to power the power transistor gate drive circuit using an inexpensive 78l05 three-ter- minal regulator. to help attenuate high frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass fi lter with the regulators input bypass capacitor. in some other applications a dedicated supply might be required to supply the vdd1. these applications include photovoltaic (pv) inverter voltage tracking and measure- ment, temperature sensor signal isolation. in these cases it is possible to add an additional winding on an existing transformer. otherwise, some sort of simple isolated supply can be used, such as a line powered transformer or a high-frequency dc-dc converter module. as shown in figure 22, 100 nf bypass capacitors (c2, c3) should be located as close as possible to the pins of the isolation amplifi er. the bypass capacitors are required because of the high-speed digital nature of the signals inside the isolation amplifi er. a 100 pf bypass capacitor (cin) is also recommended at the input pins due to the switched-capacitor nature of the input circuit. the input bypass capacitor cin also forms part of the anti-aliasing fi lter, which is recommended to prevent high-frequency noise from aliasing down to lower frequencies and inter- fering with the input signal. when r1 is far greater than r2, the low-pass anti-aliasing fi lter corner frequency can be calculated by 1/(2 ? r2cin). the input fi lter also performs an important reliability function C it reduces transient spikes from esd events fl owing through the high voltage rails. v dd1 shdn gate drive circuit 78l05 acpl-c87a cin 0.1nf c1 0.1 f c2 0.1 f gnd1 v in in out floating positive supply v out+ 5v v dd2 v out- gnd2 c3 0.1 f r1 r2 hv+ hv-
for product infor m ation and a co m plete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trade m arks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2012 avago technologies. all rights reserved. av02-3563en - july 24, 2012 pc board layout the design of the printed circuit board (pcb) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, etc. in addition, the layout of the pcb can also aff ect the isolation transient immunity (cmti) of the acpl- c87x, primarily due to stray capacitive coupling between the input and the output circuits. to obtain optimal cmti performance, the layout of the pc board should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground or power plane on the pc board does not pass directly below or extend much wider than the body of the acpl-c87a. the placement of the input capacitor which forms part of the anti-aliasing fi lter together with the resistor network should also be placed as close as possible to the vin pin.

▲Up To Search▲

Price & Availability of ACPL-C87B-500E

	To Download ACPL-C87B-500E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .